library ieee;
use ieee.std_logic_1164.all;

entity ADDRESS_DECODER_TEST is
end ADDRESS_DECODER_TEST;

architecture BEHAV of ADDRESS_DECODER_TEST is
  component address_decoder
    port (ADDRESS : in std_logic_vector;
          CHECK : in std_logic_vector(5 downto 0);
          SEL : out std_logic);
  end component;
  signal ADDR : std_logic_vector(8 to 15) := "10001010";
  signal CHECK : std_logic_vector(5 downto 0) := "1000--";
  signal SEL : std_logic;
begin
  U1: ADDRESS_DECODER port map (ADDR, CHECK, SEL);
end BEHAV;