library ieee;
use ieee.std_logic_1164.all;

entity OR_DEL is
  generic (TPLH, TPHL : time := 2 ns);
  port (x, y : in std_logic;
        f    : out std_logic);
end OR_DEL;

architecture BEHAV of OR_DEL is
begin
  process (x,y)
    variable current, old : std_logic;
  begin
    current := x or y;
    f <= x or y;
    if (current = '1' and old = '0') then
      f <= x or y after TPHL;
    elsif (current = '0' and old = '1') then
      f <= x or y after TPLH;
    end if;
    old := current;
  end process;
end BEHAV;