package LOGIC_PKG is
  component AND2_OP 
    port (A, B : in BIT; Z : out BIT);
  end component;
  component NAND2_OP 
    port (A, B : in BIT; Z : out BIT);
  end component;
  component OR4_OP 
    port (A, B, C, D : in BIT; Z : out BIT);
  end component;
end LOGIC_PKG;

use work.LOGIC_PKG.ALL;

entity EXPRESSION is
  port (A, B, C, D : in BIT;
        F : out BIT);
end EXPRESSION;

architecture STRUCTURAL of EXPRESSION is
  signal temp : bit_vector (0 to 8);
begin
  U1 : NAND2_OP port map (A, A, TEMP(0));
  U2 : NAND2_OP port map (B, B, TEMP(1));
  U3 : NAND2_OP port map (C, C, TEMP(2));
  U4 : AND2_OP port map (TEMP(0), TEMP(1), TEMP(3));
  U5 : AND2_OP port map (TEMP(2), C, TEMP(4));
  U6 : AND2_OP port map (TEMP(3), D, TEMP(5));
  U7 : AND2_OP port map (A, B, TEMP(6));
  U8 : AND2_OP port map (TEMP(5), C, TEMP(7));
  U9 : AND2_OP port map (TEMP(1), TEMP(2), TEMP(8));
  U10 : OR4_OP port map (TEMP(4), TEMP(6), TEMP(8), '0', F);
end STRUCTURAL;