package LOGIC_PKG is
  component AND2_OP
    port (A, B : in BIT; Z : out BIT);
  end component;
  component NOR2_OP
    port (A, B : in BIT; Z : out BIT);
  end component;
  component OR4_OP
    port (A, B, C, D : in BIT; Z : out BIT);
  end component;
end LOGIC_PKG;

  entity AND2_OP is
    port (A, B : in BIT; Z : out BIT);
  end AND2_OP;

  architecture AND2_OP of AND2_OP is
  begin
    Z <= A and B;
  end AND2_OP;

  entity NOR2_OP is
    port (A, B : in BIT; Z : out BIT);
  end NOR2_OP; 

  architecture NOR2_OP of NOR2_OP is
  begin
    Z <= A nor B;
  end NOR2_OP;

  entity OR4_OP is
    port (A, B, C, D : in BIT; Z : out BIT);
  end OR4_OP;

  architecture OR4_OP of OR4_OP is
  begin
    Z <= A or B or C or D;
  end OR4_OP;