library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity UPCOUNT is
  generic (N : integer);
  port (CLOCK, RESETN, E : in std_logic;
        Q                : out std_logic_vector (N - 1 downto 0));
end UPCOUNT;

architecture BEHAVIOR of UPCOUNT is
  signal COUNT : std_logic_vector (N - 1 downto 0);
begin
  process (CLOCK, RESETN)
  begin
    if (RESETN = '0') then
      COUNT <= (others => '0');
    elsif (CLOCK'event and CLOCK = '1') then
      if (E = '1') then
        COUNT <= COUNT + 1;
      else
        COUNT <= COUNT;
      end if;
    end if;
  end process;
  Q <= COUNT;
end BEHAVIOR;