library ieee;
use ieee.std_logic_1164.all;

entity IF2TO4 is
  port (A, B : in std_logic;
        EN   : in std_logic;
        C    : out std_logic_vector (3 downto 0));
end IF2TO4;

architecture IF2TO4 of IF2TO4 is
begin
  process (A, B)
  begin
    if (EN = '1') then
      if (A = '0' and B = '0') then
        C <= "0001";
      elsif (A = '0' and B = '1') then
        C <= "0010";
      elsif (A = '1' and B = '0') then
        C <= "0100";
      elsif (A = '1' and B = '1') then
        C <= "1000";
      end if;
    else
      C <= "0000";
    end if;
  end process;
end IF2TO4;

library ieee;
use ieee.std_logic_1164.all;

entity IF3TO8 is
  port (A, B, C : in std_logic;
        D       : out std_logic_vector (7 downto 0));
end IF3TO8;

architecture IF3TO8 of IF3TO8 is
  component IF2TO4C
    port (A, B : in std_logic;
          EN   : std_logic;
          C    : out std_logic_vector (3 downto 0));
  end component;
  for all : IF2TO4C use entity work.IF2TO4(IF2TO4);
  signal C_NOT : std_logic;
begin
  U1 : IF2TO4C port map (A, B, C, D(7 downto 4));
  U2 : IF2TO4C port map (A, B, C_NOT, D(3 downto 0));

  C_NOT <= not C;
end IF3TO8;