library ieee;
use ieee.std_logic_1164.all;

entity SN7400 is
generic (TPHL, TPLH : time);
port (A, B : in std_logic;
      C    : out std_logic);
end SN7400;

architecture SN7400 of SN7400 is
  signal C_INNER : std_logic;
begin
  process (A, B)
    variable C_TEMP  : std_logic;
  begin
    C_TEMP := not (A AND B);
    if (C_INNER = '1' and C_TEMP = '0') then
      C_INNER <= C_TEMP after TPHL;
    elsif (C_INNER = '0' and C_TEMP = '1') then
      C_INNER <= C_TEMP after TPLH;
    end if;
  end process;
  C <= C_INNER;
end SN7400;