package LOGIC_PKG is
  component AND3_OP
    port (A, B, C : in BIT; Z : out BIT);
  end component;
  component NAND2_OP
    port (A, B : in BIT; Z : out BIT);
  end component;
  component OR4_OP
    port (A, B, C, D : in BIT; Z : out BIT);
  end component;
end LOGIC_PKG;

  entity AND3_OP is
    port (A, B, C : in BIT; Z : out BIT);
  end AND3_OP;

  architecture AND3_OP of AND3_OP is
  begin
    Z <= A and B and C;
  end AND3_OP;

  entity NAND2_OP is
    port (A, B : in BIT; Z : out BIT);
  end NAND2_OP; 

  architecture NAND2_OP of NAND2_OP is
  begin
    Z <= A nand B;
  end NAND2_OP;

  entity OR4_OP is
    port (A, B, C, D : in BIT; Z : out BIT);
  end OR4_OP;

  architecture OR4_OP of OR4_OP is
  begin
    Z <= A or B or C or D;
  end OR4_OP;