use work.LOGIC_PKG.all;

entity EXPRESSION is
  port (A, B, C, D : in BIT;
        F : out BIT);
end EXPRESSION;

architecture STRUCTURAL of EXPRESSION is
  signal ABAR, BBAR, CBAR, G, H, I : BIT;
begin
  U1 : NAND2_OP port map(A, A, ABAR);
  U2 : NAND2_OP port map(B, B, BBAR);
  U3 : NAND2_OP port map(C, C, CBAR);
  U4 : AND3_OP port map(ABAR, BBAR, D, G);
  U5 : AND3_OP port map(A, B, C, H);
  U6 : AND3_OP port map(BBAR, CBAR, '1', I);
  U7 : OR4_OP port map(G, H, I, '0', F);
end STRUCTURAL;