A port is a signal used in describing the interface
  of a VHDL model.
Transport delay is the delay which represents wire
  delay in VHDL.
All statements inside of a process are sequential.
For the following function call, which function will
  be called? a
'event is an example of a VHDL attribute.
An entity X, when used in another entity Y, becomes a
  component for the entity Y.
BIT_VECTOR is an example of an unconstrained array.