entity DLATCH is
  port (D, CLK, S, R : in BIT;
        Q, QB : out BIT);
end DLATCH;

architecture SYNTH of DLATCH is
begin
  process (D, CLK, S, R)
  begin
    if (S = '1') then
      Q <= '1';
      QB <= '0';
    elsif (R = '1') then
      Q <= '0';
      QB <= '1';
    elsif (CLK = '1') then
      Q <= D;
      QB <= not D;
    end if;
  end process;
end SYNTH;