ENTITY and2 IS
  PORT (a, b : IN BIT;
           c : OUT BIT);
END and2;

ARCHITECTURE and2 OF and2 IS
BEGIN
  c <= a AND b;
END and2;

ENTITY inv IS
  PORT (a : IN BIT;
        b : OUT BIT);
END inv;

ARCHITECTURE inv OF inv IS
BEGIN
  b <= NOT a;
END inv;