library ieee;
use ieee.std_logic_1164.all;

entity TP_ENCODE is
  port (D : in std_logic_vector(3 downto 0);
        X, Y, V : out std_logic);
end TP_ENCODE;
    
architecture SEQUENTIAL of TP_ENCODE is
begin
  process(D)
    variable TEMP : std_logic_vector(2 downto 0);
  begin
    case d is
      when "0000" => TEMP := "ZZ0";
      when "1000" => TEMP := "001";
      when "-100" => TEMP := "011";
      when "--10" => TEMP := "101";
      when "---1" => TEMP := "111";
      when others => TEMP := "000";
    end case;
    X <= TEMP(2);
    Y <= TEMP(1);
    V <= TEMP(0);
  end process;
end SEQUENTIAL;