use WORK.all;
library ieee;
use ieee.std_logic_1164.all;

entity TEST_BENCH is
end TEST_BENCH;

architecture CONVERTER_TEST of TEST_BENCH is
  signal RUN, CLK : BIT;
  signal PG : std_logic_vector(3 downto 0);
  signal Z : std_logic_vector(2 downto 0);

  component TP_ENCODEC
    port (D : in std_logic_vector(3 downto 0);
          X : out std_logic;
          Y : out std_logic;
          V : out std_logic);
  end component;

  component ICG
    generic (N : INTEGER; PER : TIME);
    port (START : in BIT; PGOUT : out std_logic_vector (N-1 downto 0));
  end component;
    
  for L1: TP_ENCODEC use entity TP_ENCODE(sequential);
  for L2: ICG use entity PULSE_GEN(ALG);

begin
  L1: TP_ENCODEC
    port map(D => PG, X => Z(2), Y => Z(1), V => Z(0));

  L2 : ICG
    generic map(4, 20 ns)
    port map(RUN, PG);

  process
  begin
    RUN <= '1', '0' after 10 ns;
    wait;
  end process;
end CONVERTER_TEST;