library ieee;
use ieee.std_logic_1164.all;

entity P_ENCODE is
  port (D : in std_logic_vector(3 downto 0);
        X, Y, V : out std_logic);
end P_ENCODE;

architecture CONCURRENT of P_ENCODE is
begin
    V <= '1' when (D(3) = '1') else
         '1' when (D(2) = '1') else
         '1' when (D(1) = '1') else
         '1' when (D(0) = '1') else
         '0' when (D = "0000") else
         'Z'; 
    X <= '1' when (D(3) = '1') else
         '1' when (D(2) = '1') else
         '0' when (D(1) = '1') else
         '0' when (D(0) = '1') else
         'Z'; 
    Y <= '1' when (D(3) = '1') else
         '0' when (D(2) = '1') else
         '1' when (D(1) = '1') else
         '0' when (D(0) = '1') else
         'Z'; 
end CONCURRENT;

architecture SEQUENTIAL of P_ENCODE is
begin
  process(D)
    variable TEMP : std_logic_vector(2 downto 0);
  begin
    if (D(3) = '1') then
      TEMP := "111";
    elsif (D(2) = '1') then
      TEMP := "101";
    elsif (D(1) = '1') then
      TEMP := "011";
    elsif (D(0) = '1') then
      TEMP := "001";
    elsif (D = "0000") then
      TEMP := "ZZ0";
    else
      TEMP := "ZZZ";
    end if;
    X <= TEMP(2);
    Y <= TEMP(1);
    V <= TEMP(0);
  end process;
end SEQUENTIAL;