library ieee;
use ieee.std_logic_1164.all;

entity MUX_16_TO_1 is
  port (I : in std_logic_vector(15 downto 0);
        SEL : in std_logic_vector(3 downto 0);
        O : out std_logic);
end MUX_16_TO_1;

architecture STRUCTURAL of MUX_16_TO_1 is
  component MUX_4_TO_1 is
    port (I : in std_logic_vector(3 downto 0);
          SEL : in std_logic_vector(1 downto 0);
          O : out std_logic);
  end component;
  signal INTERNAL : std_logic_vector(3 downto 0);
begin
  U1 : MUX_4_TO_1 
       port map(I => I(15 downto 12),
                SEL => SEL(1 downto 0), 
                O => INTERNAL(3));
  U2 : MUX_4_TO_1 
       port map(I => I(11 downto 8),
                SEL => SEL(1 downto 0), 
                O => INTERNAL(2));
  U3 : MUX_4_TO_1 
       port map(I => I(7 downto 4),
                SEL => SEL(1 downto 0), 
                O => INTERNAL(1));
  U4 : MUX_4_TO_1 
       port map(I => I(3 downto 0),
                SEL => SEL(1 downto 0), 
                O => INTERNAL(0));
  U5 : MUX_4_TO_1 
       port map(I(3) => INTERNAL(3),
                I(2) => INTERNAL(2),
                I(1) => INTERNAL(1),
                I(0) => INTERNAL(0),
                SEL => SEL(3 downto 2), 
                O => O);
end STRUCTURAL;