entity prob is
  port (D : inout bit);
end prob;

architecture PROB of PROB is
  signal A, B, C, E, F : bit;
begin
  P1: process (A, C)
  begin
    B <= A after 2 ns;
    E <= C after 7 ns;
  end process P1;
  C <= transport A and B 
         after 6 ns;
  P2: process (C, E)
  begin
    F <= C or E after 4 ns;
  end process P2;
  process
  begin
    A <= '1' after 5 ns, 
         '0' after 12 ns;
    wait;
  end process;
  D <= A or B or C or F after 1 ns;
end PROB;