library ieee;
use ieee.std_logic_1164.all;

entity M_N_FF is
  port (M, N, CLRn, CLK : std_logic;
        Q, QB : out std_logic);
end M_N_FF;

architecture M_N_FF of M_N_FF is
  signal TEMP : std_logic;
begin
  process(CLRn, CLK)
  begin
    if (CLRn = '0') then
      TEMP <= '0';
    elsif (CLK'event and CLK = '0') then
      if (M = '1' and N = '1') then
        TEMP <= not TEMP;
      elsif (M = '0' and N = '1') then
        TEMP <= '1';
      elsif (M = '1' and N = '0') then
        TEMP <= '0';
      end if;
    end if;
  end process;
  Q <= TEMP;
  QB <= not TEMP;
end M_N_FF;