library ieee;
use ieee.std_logic_1164.all;

entity SHIFT is
  port (PAR_IN : in std_logic_vector(15 downto 0);
        CLK, ST : std_logic;
        N : in integer range 1 to 15;
        PAR_OUT : out std_logic_vector(15 downto 0));
end SHIFT;

architecture SHIFT of SHIFT is
begin
  process(CLK)
    variable TEMP : std_logic_vector(15 downto 0);
    variable COUNT : integer range 1 to 15;
    variable READY : std_logic;
  begin
    if (CLK'event and CLK = '0') then
      if (ST = '1' and READY = '1') then
        COUNT := N;
        TEMP := PAR_IN;
        READY := '0';
      else
        if (COUNT > 0) then
          COUNT := COUNT - 1;
          TEMP := TEMP(14 downto 0) & '0';
        else
          READY := '1';
        end if;
      end if;
    end if;
    PAR_OUT <= TEMP;
  end process;
end SHIFT;