library ieee;
use ieee.std_logic_1164.all;

entity FOUR_ONES is
  port (CLK, RST, X : in std_logic;
        Z : out std_logic);
end FOUR_ONES;

architecture FOUR_ONES of FOUR_ONES is
begin
  process(CLK, RST, X)
    variable TEMP : std_logic_vector(3 downto 0);
  begin
    if (RST = '1') then
      TEMP := "0000";
    elsif (CLK'event and CLK = '1') then
      TEMP := TEMP(2 downto 0) & X;
      if (TEMP = "1111") then
        Z <= '1';
      else
        Z <= '0';
      end if;
    end if; --RST = '1'
  end process;
end FOUR_ONES;