library ieee;
use ieee.std_logic_1164.all;

entity WIDGET is
  generic (FFDEL, BUFDEL : time);
  port (S1, S3, S4 : in std_logic;
        DI : std_logic_vector(7 downto 0);
        DO : out std_logic_vector(7 downto 0));
end WIDGET;

architecture WIDGET of WIDGET is
  signal Q : std_logic_vector(7 downto 0);
begin
  B1 : block 
  begin
    Q <= DI after FFDEL when (S1 = '1' and S4 = '1') else
         "00000000" after FFDEL when (S1 = '0' and S4 = '0');
    DO <= Q after BUFDEL when (S3 = '1') else
          "ZZZZZZZZ" after BUFDEL;
  end block B1;
end WIDGET;