library ieee;
use ieee.std_logic_1164.all;

entity N_AND is
  generic (N : integer);
  port (I : in std_logic_vector(N-1 downto 0);
        O : out std_logic);
end N_AND;

architecture N_AND of N_AND is
begin
  process(I)
    variable TEMP : std_logic := '1';
  begin
    for j in I'range loop
      TEMP := TEMP and I(j);
    end loop;
    O <= TEMP;
  end process;
end N_AND;

library ieee;
use ieee.std_logic_1164.all;

entity UPPER is
end UPPER;

architecture UPPER of UPPER is
  component N_AND is
    generic (N : integer);
    port (I : in std_logic_vector(N-1 downto 0);
          O : out std_logic);
  end component;
  signal a, b, c, d, f : std_logic;
begin
  U1 : N_AND generic map (N => 4)
             port map (I(0) => a, 
                       I(1) => b,
                       I(2) => c,
                       I(3) => d,
                       O => f);
end UPPER;