Timing Analyzer report for DiceGame
Thu Mar 31 09:49:49 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Settings
  3. Timing Analyzer Summary
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tsu
  7. tco
  8. tpd
  9. th
 10. Minimum tco
 11. Minimum tpd
 12. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EPF10K30EFC256-1   ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                              ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From     ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 5.600 ns                         ; Reset    ; State~10 ;            ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.400 ns                         ; State~15 ; Roll     ; CLK        ;          ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 6.700 ns                         ; Rb       ; Roll     ;            ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.500 ns                         ; Sum[2]   ; Point[2] ;            ; CLK      ; 0            ;
; Worst-case Minimum tco       ; N/A   ; None          ; 6.200 ns                         ; State~12 ; Win      ; CLK        ;          ; 0            ;
; Worst-case Minimum tpd       ; N/A   ; None          ; 6.700 ns                         ; Rb       ; Roll     ;            ;          ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 188.68 MHz ( period = 5.300 ns ) ; Point[2] ; State~13 ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;          ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                       ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From     ; To       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 188.68 MHz ( period = 5.300 ns )               ; Point[2] ; State~13 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; 192.31 MHz ( period = 5.200 ns )               ; Point[0] ; State~13 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; 204.08 MHz ( period = 4.900 ns )               ; Point[2] ; State~14 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; 208.33 MHz ( period = 4.800 ns )               ; Point[0] ; State~14 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; 212.77 MHz ( period = 4.700 ns )               ; Point[3] ; State~13 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; 217.39 MHz ( period = 4.600 ns )               ; Point[1] ; State~13 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; 232.56 MHz ( period = 4.300 ns )               ; Point[3] ; State~14 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; 238.10 MHz ( period = 4.200 ns )               ; Point[1] ; State~14 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~15 ; State~13 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~11 ; State~12 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; Point[2] ; State~12 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~11 ; State~14 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; Point[0] ; State~12 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~11 ; Point[2] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~11 ; Point[0] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~11 ; Point[1] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~11 ; Point[3] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~12 ; State~10 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~13 ; State~10 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; Point[3] ; State~12 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~11 ; State~13 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; Point[1] ; State~12 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~13 ; State~13 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~12 ; State~12 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~15 ; State~14 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~15 ; State~12 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~14 ; State~14 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~15 ; State~15 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~14 ; State~15 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~10 ; State~10 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~11 ; State~11 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; State~10 ; State~11 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------+
; tsu                                                              ;
+-------+--------------+------------+--------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To       ; To Clock ;
+-------+--------------+------------+--------+----------+----------+
; N/A   ; None         ; 5.600 ns   ; Reset  ; State~10 ; CLK      ;
; N/A   ; None         ; 5.200 ns   ; Reset  ; State~12 ; CLK      ;
; N/A   ; None         ; 5.100 ns   ; Reset  ; State~13 ; CLK      ;
; N/A   ; None         ; 4.700 ns   ; Sum[0] ; State~14 ; CLK      ;
; N/A   ; None         ; 4.600 ns   ; Sum[0] ; State~13 ; CLK      ;
; N/A   ; None         ; 4.600 ns   ; Sum[1] ; State~14 ; CLK      ;
; N/A   ; None         ; 4.600 ns   ; Sum[2] ; State~14 ; CLK      ;
; N/A   ; None         ; 4.500 ns   ; Sum[0] ; Point[3] ; CLK      ;
; N/A   ; None         ; 4.500 ns   ; Sum[0] ; Point[1] ; CLK      ;
; N/A   ; None         ; 4.500 ns   ; Sum[0] ; Point[0] ; CLK      ;
; N/A   ; None         ; 4.500 ns   ; Sum[0] ; Point[2] ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[3] ; State~14 ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[1] ; Point[3] ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[1] ; Point[1] ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[1] ; Point[0] ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[1] ; Point[2] ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[2] ; State~13 ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[2] ; Point[3] ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[2] ; Point[1] ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[2] ; Point[0] ; CLK      ;
; N/A   ; None         ; 4.400 ns   ; Sum[2] ; Point[2] ; CLK      ;
; N/A   ; None         ; 4.200 ns   ; Sum[3] ; Point[3] ; CLK      ;
; N/A   ; None         ; 4.200 ns   ; Sum[3] ; Point[1] ; CLK      ;
; N/A   ; None         ; 4.200 ns   ; Sum[3] ; Point[0] ; CLK      ;
; N/A   ; None         ; 4.200 ns   ; Sum[3] ; Point[2] ; CLK      ;
; N/A   ; None         ; 4.200 ns   ; Sum[1] ; State~13 ; CLK      ;
; N/A   ; None         ; 4.000 ns   ; Sum[3] ; State~13 ; CLK      ;
; N/A   ; None         ; 4.000 ns   ; Sum[0] ; State~12 ; CLK      ;
; N/A   ; None         ; 3.900 ns   ; Sum[1] ; State~12 ; CLK      ;
; N/A   ; None         ; 3.900 ns   ; Sum[2] ; State~12 ; CLK      ;
; N/A   ; None         ; 3.700 ns   ; Sum[3] ; State~12 ; CLK      ;
; N/A   ; None         ; 2.700 ns   ; Rb     ; State~13 ; CLK      ;
; N/A   ; None         ; 2.600 ns   ; Rb     ; State~12 ; CLK      ;
; N/A   ; None         ; 2.500 ns   ; Rb     ; State~14 ; CLK      ;
; N/A   ; None         ; 2.300 ns   ; Rb     ; Point[3] ; CLK      ;
; N/A   ; None         ; 2.300 ns   ; Rb     ; Point[1] ; CLK      ;
; N/A   ; None         ; 2.300 ns   ; Rb     ; Point[0] ; CLK      ;
; N/A   ; None         ; 2.300 ns   ; Rb     ; Point[2] ; CLK      ;
; N/A   ; None         ; 0.900 ns   ; Rb     ; State~10 ; CLK      ;
; N/A   ; None         ; 0.700 ns   ; Rb     ; State~11 ; CLK      ;
; N/A   ; None         ; 0.700 ns   ; Rb     ; State~15 ; CLK      ;
+-------+--------------+------------+--------+----------+----------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+----------+------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To   ; From Clock ;
+-------+--------------+------------+----------+------+------------+
; N/A   ; None         ; 7.400 ns   ; State~13 ; Lose ; CLK        ;
; N/A   ; None         ; 7.400 ns   ; State~11 ; Roll ; CLK        ;
; N/A   ; None         ; 7.400 ns   ; State~15 ; Roll ; CLK        ;
; N/A   ; None         ; 6.200 ns   ; State~12 ; Win  ; CLK        ;
+-------+--------------+------------+----------+------+------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 6.700 ns        ; Rb   ; Roll ;
+-------+-------------------+-----------------+------+------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+--------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To       ; To Clock ;
+---------------+-------------+-----------+--------+----------+----------+
; N/A           ; None        ; 0.500 ns  ; Sum[3] ; Point[3] ; CLK      ;
; N/A           ; None        ; 0.500 ns  ; Sum[0] ; Point[0] ; CLK      ;
; N/A           ; None        ; 0.500 ns  ; Sum[1] ; Point[1] ; CLK      ;
; N/A           ; None        ; 0.500 ns  ; Sum[2] ; Point[2] ; CLK      ;
; N/A           ; None        ; 0.400 ns  ; Rb     ; State~11 ; CLK      ;
; N/A           ; None        ; 0.400 ns  ; Rb     ; State~15 ; CLK      ;
; N/A           ; None        ; 0.200 ns  ; Rb     ; State~10 ; CLK      ;
; N/A           ; None        ; 0.200 ns  ; Rb     ; State~12 ; CLK      ;
; N/A           ; None        ; 0.100 ns  ; Rb     ; State~14 ; CLK      ;
; N/A           ; None        ; -0.800 ns ; Rb     ; State~13 ; CLK      ;
; N/A           ; None        ; -0.900 ns ; Sum[3] ; State~12 ; CLK      ;
; N/A           ; None        ; -1.100 ns ; Sum[1] ; State~12 ; CLK      ;
; N/A           ; None        ; -1.200 ns ; Rb     ; Point[3] ; CLK      ;
; N/A           ; None        ; -1.200 ns ; Rb     ; Point[1] ; CLK      ;
; N/A           ; None        ; -1.200 ns ; Rb     ; Point[0] ; CLK      ;
; N/A           ; None        ; -1.200 ns ; Rb     ; Point[2] ; CLK      ;
; N/A           ; None        ; -1.400 ns ; Sum[3] ; State~13 ; CLK      ;
; N/A           ; None        ; -1.500 ns ; Sum[2] ; State~12 ; CLK      ;
; N/A           ; None        ; -1.600 ns ; Sum[0] ; State~13 ; CLK      ;
; N/A           ; None        ; -1.600 ns ; Sum[2] ; State~13 ; CLK      ;
; N/A           ; None        ; -1.700 ns ; Sum[0] ; State~12 ; CLK      ;
; N/A           ; None        ; -1.700 ns ; Sum[1] ; State~13 ; CLK      ;
; N/A           ; None        ; -2.300 ns ; Sum[3] ; State~14 ; CLK      ;
; N/A           ; None        ; -2.500 ns ; Sum[3] ; Point[1] ; CLK      ;
; N/A           ; None        ; -2.500 ns ; Sum[3] ; Point[0] ; CLK      ;
; N/A           ; None        ; -2.500 ns ; Sum[3] ; Point[2] ; CLK      ;
; N/A           ; None        ; -2.500 ns ; Sum[1] ; State~14 ; CLK      ;
; N/A           ; None        ; -2.700 ns ; Sum[0] ; Point[3] ; CLK      ;
; N/A           ; None        ; -2.700 ns ; Sum[0] ; Point[1] ; CLK      ;
; N/A           ; None        ; -2.700 ns ; Sum[0] ; Point[2] ; CLK      ;
; N/A           ; None        ; -2.700 ns ; Sum[2] ; Point[3] ; CLK      ;
; N/A           ; None        ; -2.700 ns ; Sum[2] ; Point[1] ; CLK      ;
; N/A           ; None        ; -2.700 ns ; Sum[2] ; Point[0] ; CLK      ;
; N/A           ; None        ; -2.800 ns ; Sum[0] ; State~14 ; CLK      ;
; N/A           ; None        ; -2.800 ns ; Sum[1] ; Point[3] ; CLK      ;
; N/A           ; None        ; -2.800 ns ; Sum[1] ; Point[0] ; CLK      ;
; N/A           ; None        ; -2.800 ns ; Sum[1] ; Point[2] ; CLK      ;
; N/A           ; None        ; -2.900 ns ; Sum[2] ; State~14 ; CLK      ;
; N/A           ; None        ; -4.000 ns ; Reset  ; State~13 ; CLK      ;
; N/A           ; None        ; -4.100 ns ; Reset  ; State~12 ; CLK      ;
; N/A           ; None        ; -4.500 ns ; Reset  ; State~10 ; CLK      ;
+---------------+-------------+-----------+--------+----------+----------+


+----------------------------------------------------------------------------------+
; Minimum tco                                                                      ;
+---------------+------------------+----------------+----------+------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From     ; To   ; From Clock ;
+---------------+------------------+----------------+----------+------+------------+
; N/A           ; None             ; 6.200 ns       ; State~12 ; Win  ; CLK        ;
; N/A           ; None             ; 7.400 ns       ; State~15 ; Roll ; CLK        ;
; N/A           ; None             ; 7.400 ns       ; State~11 ; Roll ; CLK        ;
; N/A           ; None             ; 7.400 ns       ; State~13 ; Lose ; CLK        ;
+---------------+------------------+----------------+----------+------+------------+


+-------------------------------------------------------------------+
; Minimum tpd                                                       ;
+---------------+-------------------+-----------------+------+------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+---------------+-------------------+-----------------+------+------+
; N/A           ; None              ; 6.700 ns        ; Rb   ; Roll ;
+---------------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu Mar 31 09:49:43 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off DiceGamea -c DiceGame
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node CLK is an undefined clock
Info: Clock CLK has Internal fmax of 188.68 MHz between source register Point[2] and destination register State~13 (period= 5.3 ns)
    Info: + Longest register to register delay is 4.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C2; Fanout = 1; REG Node = 'Point[2]'
        Info: 2: + IC(0.100 ns) + CELL(0.700 ns) = 0.800 ns; Loc. = LC2_C2; Fanout = 1; COMB Node = 'reduce_nor~66'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 1.800 ns; Loc. = LC3_C2; Fanout = 3; COMB Node = 'reduce_nor~68'
        Info: 4: + IC(0.400 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC7_C1; Fanout = 1; COMB Node = 'Nextstate.s3~102'
        Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 4.100 ns; Loc. = LC8_C1; Fanout = 1; COMB Node = 'Nextstate.s3~103'
        Info: 6: + IC(0.100 ns) + CELL(0.400 ns) = 4.600 ns; Loc. = LC6_C1; Fanout = 3; REG Node = 'State~13'
        Info: Total cell delay = 3.900 ns ( 84.78 % )
        Info: Total interconnect delay = 0.700 ns ( 15.22 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock CLK to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 10; CLK Node = 'CLK'
            Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC6_C1; Fanout = 3; REG Node = 'State~13'
            Info: Total cell delay = 1.300 ns ( 86.67 % )
            Info: Total interconnect delay = 0.200 ns ( 13.33 % )
        Info: - Longest clock path from clock CLK to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 10; CLK Node = 'CLK'
            Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC5_C2; Fanout = 1; REG Node = 'Point[2]'
            Info: Total cell delay = 1.300 ns ( 86.67 % )
            Info: Total interconnect delay = 0.200 ns ( 13.33 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Micro setup delay of destination is 0.400 ns
Info: tsu for register State~10 (data pin = Reset, clock pin = CLK) is 5.600 ns
    Info: + Longest pin to register delay is 6.700 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_H12; Fanout = 3; PIN Node = 'Reset'
        Info: 2: + IC(1.900 ns) + CELL(0.800 ns) = 5.500 ns; Loc. = LC1_C1; Fanout = 1; COMB Node = 'Nextstate.s0~14'
        Info: 3: + IC(0.800 ns) + CELL(0.400 ns) = 6.700 ns; Loc. = LC4_C9; Fanout = 2; REG Node = 'State~10'
        Info: Total cell delay = 4.000 ns ( 59.70 % )
        Info: Total interconnect delay = 2.700 ns ( 40.30 % )
    Info: + Micro setup delay of destination is 0.400 ns
    Info: - Shortest clock path from clock CLK to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 10; CLK Node = 'CLK'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_C9; Fanout = 2; REG Node = 'State~10'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
Info: tco from clock CLK to destination pin Lose through register State~13 is 7.400 ns
    Info: + Longest clock path from clock CLK to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 10; CLK Node = 'CLK'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC6_C1; Fanout = 3; REG Node = 'State~13'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Longest register to pin delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_C1; Fanout = 3; REG Node = 'State~13'
        Info: 2: + IC(1.800 ns) + CELL(3.800 ns) = 5.600 ns; Loc. = PIN_H13; Fanout = 0; PIN Node = 'Lose'
        Info: Total cell delay = 3.800 ns ( 67.86 % )
        Info: Total interconnect delay = 1.800 ns ( 32.14 % )
Info: Longest tpd from source pin Rb to destination pin Roll is 6.700 ns
    Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_B9; Fanout = 9; PIN Node = 'Rb'
    Info: 2: + IC(0.100 ns) + CELL(0.800 ns) = 2.200 ns; Loc. = LC1_C9; Fanout = 1; COMB Node = 'Select~22'
    Info: 3: + IC(0.700 ns) + CELL(3.800 ns) = 6.700 ns; Loc. = PIN_G1; Fanout = 0; PIN Node = 'Roll'
    Info: Total cell delay = 5.900 ns ( 88.06 % )
    Info: Total interconnect delay = 0.800 ns ( 11.94 % )
Info: th for register Point[3] (data pin = Sum[3], clock pin = CLK) is 0.500 ns
    Info: + Longest clock path from clock CLK to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 10; CLK Node = 'CLK'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC7_C2; Fanout = 1; REG Node = 'Point[3]'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
    Info: + Micro hold delay of destination is 0.700 ns
    Info: - Shortest pin to register delay is 1.700 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_E8; Fanout = 5; PIN Node = 'Sum[3]'
        Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 1.700 ns; Loc. = LC7_C2; Fanout = 1; REG Node = 'Point[3]'
        Info: Total cell delay = 1.700 ns ( 100.00 % )
Info: Minimum tco from clock CLK to destination pin Win through register State~12 is 6.200 ns
    Info: + Shortest clock path from clock CLK to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 10; CLK Node = 'CLK'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_C1; Fanout = 3; REG Node = 'State~12'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Shortest register to pin delay is 4.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C1; Fanout = 3; REG Node = 'State~12'
        Info: 2: + IC(0.600 ns) + CELL(3.800 ns) = 4.400 ns; Loc. = PIN_H4; Fanout = 0; PIN Node = 'Win'
        Info: Total cell delay = 3.800 ns ( 86.36 % )
        Info: Total interconnect delay = 0.600 ns ( 13.64 % )
Info: Shortest tpd from source pin Rb to destination pin Roll is 6.700 ns
    Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_B9; Fanout = 9; PIN Node = 'Rb'
    Info: 2: + IC(0.100 ns) + CELL(0.800 ns) = 2.200 ns; Loc. = LC1_C9; Fanout = 1; COMB Node = 'Select~22'
    Info: 3: + IC(0.700 ns) + CELL(3.800 ns) = 6.700 ns; Loc. = PIN_G1; Fanout = 0; PIN Node = 'Roll'
    Info: Total cell delay = 5.900 ns ( 88.06 % )
    Info: Total interconnect delay = 0.800 ns ( 11.94 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Mar 31 09:49:49 2005
    Info: Elapsed time: 00:00:06


