Analysis & Synthesis report for DiceGame
Thu Mar 31 09:48:38 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Hierarchy
  5. State Machine - State
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis Equations
  8. Analysis & Synthesis Source Files Read
  9. Analysis & Synthesis Resource Usage Summary
 10. WYSIWYG Cells
 11. General Register Statistics
 12. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+---------------------------------------------------------------------+
; Analysis & Synthesis Summary                                        ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Mar 31 09:48:38 2005 ;
; Quartus II Version          ; 4.1 Build 181 06/29/2004 SJ           ;
; Revision Name               ; DiceGame                              ;
; Top-level Entity Name       ; DiceGame                              ;
; Family                      ; FLEX10KE                              ;
; Total logic elements        ; 23                                    ;
; Total pins                  ; 10                                    ;
; Total memory bits           ; 0                                     ;
; Total PLLs                  ; 0                                     ;
+-----------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                           ;
+------------------------------------------------------+------------------+---------------+
; Option                                               ; Setting          ; Default Value ;
+------------------------------------------------------+------------------+---------------+
; Device                                               ; EPF10K30EFC256-1 ;               ;
; Family name                                          ; FLEX10KE         ; Stratix       ;
; Create Debugging Nodes for IP Cores                  ; off              ; off           ;
; Disk space/compilation speed tradeoff                ; Normal           ; Normal        ;
; Preserve fewer node names                            ; On               ; On            ;
; Disable OpenCore Plus hardware evaluation            ; Off              ; Off           ;
; Verilog Version                                      ; Verilog_2001     ; Verilog_2001  ;
; VHDL Version                                         ; VHDL93           ; VHDL93        ;
; Top-level entity name                                ; DiceGame         ; DiceGame      ;
; State Machine Processing                             ; Auto             ; Auto          ;
; NOT Gate Push-Back                                   ; On               ; On            ;
; Power-Up Don't Care                                  ; On               ; On            ;
; Remove Redundant Logic Cells                         ; Off              ; Off           ;
; Remove Duplicate Registers                           ; On               ; On            ;
; Ignore CARRY Buffers                                 ; Off              ; Off           ;
; Ignore CASCADE Buffers                               ; Off              ; Off           ;
; Ignore GLOBAL Buffers                                ; Off              ; Off           ;
; Ignore ROW GLOBAL Buffers                            ; Off              ; Off           ;
; Ignore LCELL Buffers                                 ; Off              ; Off           ;
; Ignore SOFT Buffers                                  ; On               ; On            ;
; Limit AHDL Integers to 32 Bits                       ; Off              ; Off           ;
; Auto Implement in ROM                                ; Off              ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area             ; Area          ;
; Carry Chain Length -- FLEX 10K                       ; 32               ; 32            ;
; Cascade Chain Length                                 ; 2                ; 2             ;
; Auto Carry Chains                                    ; On               ; On            ;
; Auto Open-Drain Pins                                 ; On               ; On            ;
; Remove Duplicate Logic                               ; On               ; On            ;
; Auto ROM Replacement                                 ; On               ; On            ;
; Auto RAM Replacement                                 ; On               ; On            ;
; Auto Clock Enable Replacement                        ; On               ; On            ;
; Auto Resource Sharing                                ; Off              ; Off           ;
; Allow Any RAM Size For Recognition                   ; Off              ; Off           ;
; Allow Any ROM Size For Recognition                   ; Off              ; Off           ;
+------------------------------------------------------+------------------+---------------+


+-----------+
; Hierarchy ;
+-----------+
DiceGame


+----------------------------------------------------------------------------+
; State Machine - State                                                      ;
+----------+----------+----------+----------+----------+----------+----------+
; Name     ; State~15 ; State~14 ; State~13 ; State~12 ; State~11 ; State~10 ;
+----------+----------+----------+----------+----------+----------+----------+
; State.s0 ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ;
; State.s1 ; 0        ; 0        ; 0        ; 0        ; 1        ; 1        ;
; State.s2 ; 0        ; 0        ; 0        ; 1        ; 0        ; 1        ;
; State.s3 ; 0        ; 0        ; 1        ; 0        ; 0        ; 1        ;
; State.s4 ; 0        ; 1        ; 0        ; 0        ; 0        ; 1        ;
; State.s5 ; 1        ; 0        ; 0        ; 0        ; 0        ; 1        ;
+----------+----------+----------+----------+----------+----------+----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
; |DiceGame                  ; 23 (23)     ; 10           ; 0           ; 10   ; 13 (13)      ; 4 (4)             ; 6 (6)            ; 0 (0)           ; |DiceGame           ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in /home/faculty/gaede/public_html/cpe422/book_vhdl/Chap05/dice_game_quartus/DiceGame.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+---------------+------------------------+
; File Name     ; Used in Netlist        ;
+---------------+------------------------+
; dice_game.vhd ; yes                    ;
+---------------+------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Logic cells                     ; 23        ;
; Total combinational functions   ; 19        ;
; Total 4-input functions         ; 11        ;
; Total 3-input functions         ; 7         ;
; Total 2-input functions         ; 1         ;
; Total 1-input functions         ; 0         ;
; Total 0-input functions         ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 10        ;
; I/O pins                        ; 10        ;
; Maximum fan-out node            ; CLK       ;
; Maximum fan-out                 ; 10        ;
; Total fan-out                   ; 89        ;
; Average fan-out                 ; 2.70      ;
+---------------------------------+-----------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 23    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 19    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 10    ;
; Number of cells with combinational logic only          ; 13    ;
; Number of cells with registers only                    ; 4     ;
; Number of cells with combinational logic and registers ; 6     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu Mar 31 09:48:27 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off DiceGamea -c DiceGame
Info: Found 2 design units, including 1 entities, in source file dice_game.vhd
    Info: Found design unit 1: DiceGame-DiceBehave
    Info: Found entity 1: DiceGame
Warning: VHDL Process Statement warning at dice_game.vhd(56): signal point is in statement, but is not in sensitivity list
Info: State machine |DiceGame|State contains 6 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |DiceGame|State
Info: Encoding result for state machine |DiceGame|State
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit State~15
        Info: Encoded state bit State~14
        Info: Encoded state bit State~13
        Info: Encoded state bit State~12
        Info: Encoded state bit State~11
        Info: Encoded state bit State~10
    Info: State |DiceGame|State.s0 uses code string 000000
    Info: State |DiceGame|State.s1 uses code string 000011
    Info: State |DiceGame|State.s2 uses code string 000101
    Info: State |DiceGame|State.s3 uses code string 001001
    Info: State |DiceGame|State.s4 uses code string 010001
    Info: State |DiceGame|State.s5 uses code string 100001
Info: Implemented 33 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 3 output pins
    Info: Implemented 23 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Mar 31 09:48:38 2005
    Info: Elapsed time: 00:00:10


