[WindowState] SaveWin=0x00000000 Open Documents=0x00000000 [System] CWD=/home/faculty/gaede/public_html/cpe422/book_vhdl/Chap05 [Verilog] Top Module= Parameters= Full Case=0x00000000 Parallel Case=0x00000000 [VHDL] Top Module= Arch= Generic= VHDL Style=0x00000000 [XNF] Preserve Dangle=0x00000000 Preserve GSR=0x00000000 Preserve GTS=0x00000000 Preserve Pin Loc=0x00000001 [SDF] SDF Hierarchy=0x00000001 SDF Type=0x00000002 [EDIF] Design= [Verilog Out] Allow Buses=0x00000001 [VHDL Out] Write Bit Type=std_logic Write Vector Type=std_logic_vector VHDL Write Style=0x00000000 Allow Buses=0x00000001 [SDF Out] SDF Name Style=0x00000000 Write Flat Netlist=0x00000000 [EDIF Out] Gnd=GND Power=VCC Allow Buses=0x00000001 PwrNGnd Is Net=0x00000000 Write Dont Touch=0x00000000 [Files] InputFileCount=1 InputFile0=/home/faculty/gaede/public_html/cpe422/book_vhdl/Chap05/dice_game.vhd;work;0;Undetermined; OutputFile=/home/faculty/gaede/public_html/cpe422/book_vhdl/Chap05/dice_game_0.vhd Run Elaborate=0x00000001 Run PreOpt=0x00000001 InputFormat=0x00000000 OutputFormat=0x00000001 WriteCnstrntFile=0x00000001 PreProcess=0x00000001 WriteTopOnly=0x00000000 WriteModules=0x00000000 Downto=0x00000000 [File Options] no opt= Search Path= [RunTime] Optimization=0x00000002 Report=0x00000001 Preserve Hier=0x00000000 Resource Sharing=0x00000001 SingleLevel=0x00000000 OTSingleLevel=0x00000000 OTForce=0x00000000 Run Type=0x00000000 CPU Limit=0x00000000 Extended=0x00000000 Pass 1=0x00000001 Pass 2=0x00000001 Pass 3=0x00000001 Pass 4=0x00000001 Break Combo=0x00000000 Convert 3 State=0x00000000 No Wire Table=0x00000000 Transform SR=0x00000001 Bubble Tristates=0x00000001 Run Timing Opt=0x00000001 Run Integrated PnR=0x00000000 Run TimeCloser=0x00000000 Enable TrueTiming=0x00000000 Autodissolve Limit=0x00000032 Asic Autodissolve Limit=0x0000001E [FSM] Encoding=0x00000002 [Report Opts] Path Detail=0x00000000 Wire Tree=0x00000000 Max Slack=1000.000000 Max Arr=0 Wire Table= From Paths= To Paths= Through Paths= Not Through Paths= Path Numbers=1 CD in ID=0x00000000 No Intern Terminal=0x00000000 No IO Terminal=0x00000000 Report Input=0x00000000 Report Net=0x00000000 Show Clock=0x00000001 Sort by Delay=0x00000000 Show Schematic=0x00000000 Report File= [ReportArea] Filename= CellUsage=0x00000001 Hierarchy=0x00000000 Leafs=0x00000001 [Modgen] Operators=0x00000000 Clock Enable=0x00000001 Counters=0x00000001 Decoders=0x00000001 Modgen On=0x00000001 RAM=0x00000001 ROM=0x00000001 [PreOpt] ShareCommon=0x00000001 RemoveUnused=0x00000001 Extract=0x00000001 WideOpt=0x00000001 SingleLevel=0x00000000 Boundary=0x00000001 [Xilinx PnR] Exec Path= Env Variable=$XILINX/bin/sol Exec Type=0x00000000 NCD File= UCF File= Bitgen File= Effort=0x00000001 Simulation Output Format=0x00000000 Guide Mode=0x00000001 Use Bitfile=0x00000000 Use time file=0x00000000 Use bitgen=0x00000000 Back anotate=0x00000001 Backannotated Simulation=0x00000001 Run Design Planner=0x00000001 Run View Placement=0x00000001 Run GUI=0x00000000 Use Guide File=0x00000000 Use NCD File=0x00000000 [Altera Pnr] Exec Path= Env Variable=$MAX2_HOME/bin Fast IO=0x00000000 Implement EAB=0x00000000 Input to Output Delay=0x00000000 Overright ACF=0x00000000 Register Packing=0x00000000 Run Max=0x00000001 Run Max GUI=0x00000000 Run SetupHold=0x00000002 Setup Max=0x00000001 Timing Analysis=0x00000001 Backannotated Simulation=0x00000001 Simulation Output Format=0x00000000 [Quartus Pnr] Exec Path= Env Variable=$QUARTUS_ROOTDIR/bin Run Quartus=0x00000001 Run Quartus GUI=0x00000000 Backannotated Simulation=0x00000001 Simulation Output Format=0x00000000 Compile Design=0x00000001 [Lattice Pnr] Exec Path= Env Variable=$DDIRECT/ispcomp/bin Run DesignDirect=0x00000001 Run DesignDirect GUI=0x00000001 [Schematic Viewer] Show Commands=0x00000000 Expand Buses=0x00000000 AutoGroup Bused Instances=0x00000000 Show Multiple Pages=0x00000001 Show Hierarchy=0x00000000 Query Mode=0x00000001 Select Ports=0x00000001 Select Nets=0x00000001 Select Instances=0x00000001 Select Pins=0x00000001 Zoom Area Mode=0x00000001 Overlapcolor=0x008C8C8C Rubberbandcolor=0x000000FF Backgroundcolor=0x00FFFFFF Boxcolor0=0x00FF0000 Boxcolor1=0x00808000 Boxcolor2=0x00808000 Boxcolor3=0x00804000 Boxpincolor=0x00808040 Boxinstcolor=0x008000FF Netcolor=0x00000000 Buscolor=0x00804000 Portcolor=0x00A00000 Attrcolor=0x00FFFFFF Framecolor=0x00A1A1A1 Rippercolor=0x00A00000 Objectgrey=0x007F7F7F Objecthighlight0=0x000000FF Objecthighlight1=0x000000FF Objecthighlight2=0x000000FF Objecthighlight3=0x000000FF Objecthighlight4=0x000000FF Objecthighlight5=0x000000FF Objecthighlight6=0x000000FF Objecthighlight7=0x000000FF Objecthighlight8=0x000000FF Objecthighlight9=0x000000FF Showcellname=0x00000001 Showinstname=0x00000000 Showpinname=0x00000001 ShowHierpinname=0x00000000 Showattribute=0x00000001 Shownetname=0x00000001 Showinvisibles=0x00000001 Boxfontsize=0.000000 Boxpinfontsize=0.000000 Boxinstfontsize=0.000000 Netfontsize=0.000000 Busfontsize=0.000000 Attrfontsize=0.000000 Framefontsize=0.000000 Gatecellname=0.000000 Gatepinname=0.000000 Pinpermute=0x00000001 Placeiobuffer=0x00000001 Powerground=0x00000001 Latchfblevel=0.000000 Outfblevel=0.000000 Sheetwidth=8.500000 Sheetheight=11.000000 Fitpage=0x00000000 Boxpingrid=0.000000 Boxminwidth=0.000000 Boxminheight=0.000000 Boxmaxwidth=0.000000 Grid=0.000000 Largenet=0.000000 Instattrmax=0.000000 Pinattrmax=0.000000 Boxmingap=0.000000 Timelimit=0.000000 Closeenough=0.000000 Hierarchygoup=0x00000000 Instdrag=0.000000 Selectbycolor9=0x00000000 Selectattr=0.000000 Hiattrvalue=0x00000000 FlyingSegments=0x00000000 Logfile= MaxZoom=1.990000 [Elab] Params= Generics= WorkLib= TopOnly=0x00000000 [Device] Current Manufacturer=Altera Current Family=FLEX 10KE Speed=0x00000000 Part=0x00000017 Package=0x00000000 WireList=0x00000000 Voltage= Temperature= CIM= BTW= Max PT=0 Max FanOut=0.000000 Max FanIn=0 LUT Max FanOut=0 Max CapLoad=0.000000 Force User Load Values=0x00000000 Global SR= Exclude GatesCount=0 Include Gates= Preference File= Fd1s3ix=0x00000000 Fd1s1j=0x00000000 Fd1s3jx=0x00000000 Fd1s1i=0x00000000 Fd1p3jz=0x00000000 Fd1p3iz=0x00000000 Fl1p3jz=0x00000000 Fl1p3iz=0x00000000 Pack Logic to CLB=0x00000000 Write HBLKNM=0x00000000 Use Fast=0x00000000 Use F5MAPSYM=0x00000000 Quad Clock Buffers=0x00000000 Map LUT=0x00000001 Map Complex IO=0x00000001 Map Clock Buffers=0x00000001 Map Cascades=0x00000001 Altera use Add Carry Sum=0x00000001 Flex Lock LCells=0x00000001 Max Lock LCells=0x00000000 Write EQN=0x00000001 AutoGSR=0x00000001 ManGSR=0x00000000 Infer 6LUT=0x00000000 Generate TimeSpec=0x00000000 DoLogicRepl=0x00000001 AddIOPads=0x00000001 Use Lowskew=0x00000000 Map IOB Registers=0x00000000 Map Altera IO Registers=0x00000000 Implement RAM in ESB=0x00000000 Map MUXF5=0x00000001 Map MUXF6=0x00000001 Use Clock MUX=0x00000000 Map 18x18=0x00000001 Use extended mach flow=0x00000000 Write Lut Binding=0x00000001 Extract MAC=0x00000001 Extract SRL=0x00000001 [Global Constraints] Clock Freq=10 Clock Period=100 Input Port 2 Register=100 Register 2 Register=100 Register 2 Output=100 Input 2 Output= Which Group=0x00000000