entity SR_LATCH is
  port (S, R : in bit;
        Q, QBAR : inout bit);
end SR_LATCH;

architecture CONDITIONAL of SR_LATCH is
begin
  Q <= '1' when S = '1' else
       '1' when R = '0' and Q = '1' else
       '0';
  QBAR <= not Q;
end CONDITIONAL;

architecture CHARACTERISTIC of SR_LATCH is
begin
  Q <= S or (not R and Q);
  QBAR <= not Q;
end CHARACTERISTIC;

entity NOR_GATE_2 is
  port (I0, I1 : in bit;
        O : out bit);
end NOR_GATE_2;

architecture BEHAV of NOR_GATE_2 is
begin
  O <= not (I1 or I0);
end BEHAV;

architecture GATES of SR_LATCH is
  component NOR_GATE_2
    port (I0, I1 : in bit;
          O : out bit);
  end component;
  for ALL : NOR_GATE_2 use entity work.NOR_GATE_2(BEHAV);
begin
  NOR0 : NOR_GATE_2 port map (S, Q, QBAR);
  NOR1 : NOR_GATE_2 port map (R, QBAR, Q);
end GATES;