entity PLUS_TWO is
  port (X, CLK : in bit;
        SV : out bit_vector(1 downto 0));
end PLUS_TWO;

architecture ARRAY_MODEL of PLUS_TWO is
  type STATE_TABLE is array (integer range <>, bit range <>) of integer;
  type OUT_TABLE is array (integer range <>, bit range <>) of bit_vector (1 downto 0);
  signal STATE, NEXT_STATE : integer := 0;
  constant ST : STATE_TABLE (0 to 5, '0' to '1') :=
                ((1, 1), (2, 3), (4, 4), (4, 5), (0, 0), (0, 0));
  constant OT : OUT_TABLE (0 to 5, '0' to '1') :=
                (("00", "10"), ("10", "00"), ("00", "10"),
                 ("10", "00"), ("00", "10"), ("11", "01"));
begin
  NEXT_STATE <= ST(STATE, X);
  SV <= OT(STATE, X);

  process (CLK)
  begin
    if (CLK = '0' and CLK'event) then
      STATE <= NEXT_STATE;
    end if;
  end process;
end ARRAY_MODEL;

entity PLUS_TWO_TEST is
end PLUS_TWO_TEST;

architecture BEHAV of PLUS_TWO_TEST is
  component PLUS_TWO
    port (X, CLK : in bit;
          SV : out bit_vector (1 downto 0));
  end component;
  for ALL : PLUS_TWO use entity work.PLUS_TWO(ARRAY_MODEL);
  signal X, CLK : bit := '0';
  signal SV : bit_vector (1 downto 0);
begin
  UUT : PLUS_TWO port map (X, CLK, SV);
  CLK <= not CLK after 20 ns;
  process
  begin
    X <= '1' after 10 ns, '1' after 50 ns, '0' after 90 ns,
         '1' after 130 ns, '1' after 170 ns, '1' after 210 ns,
         '1' after 250 ns, '0' after 290 ns, '1' after 330 ns,
         '1' after 370 ns, '1' after 410 ns, '1' after 450 ns;
    wait;
  end process;
end BEHAV;