entity FULL_SUB is
  port (X, Y, BIN : in bit;
        SUM, BOUT : out bit);
end FULL_SUB;

architecture EQUATIONS of FULL_SUB is
begin
  SUM <= (X and not Y and not BIN) or (not X and not Y and BIN) or
         (X and Y and BIN) or (not X and Y and not BIN);
  BOUT <= (not X and BIN) or (not X and Y) or (Y and BIN);
end EQUATIONS;

entity SUB4 is
  port (A, B : in bit_vector (3 downto 0); BIN : in bit;
        S: out bit_vector (3 downto 0); BOUT : out bit);
end SUB4;

architecture STRUCTURAL of SUB4 is
  component FULL_SUB 
    port (X, Y, BIN : in bit;
          SUM, BOUT : out bit);
  end component;
  for ALL : FULL_SUB use entity work.FULL_SUB(EQUATIONS);
  signal BORROW : bit_vector (3 downto 1);
begin
  FS0 : FULL_SUB port map (A(0), B(0), BIN, S(0), BORROW(1));
  FS1 : FULL_SUB port map (A(1), B(1), BORROW(1), S(1), BORROW(2));
  FS2 : FULL_SUB port map (A(2), B(2), BORROW(2), S(2), BORROW(3));
  FS3 : FULL_SUB port map (A(3), B(3), BORROW(3), S(3), BOUT);
end STRUCTURAL;